1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for aligning micro patterns of a semiconductor device, capable of reducing the number of dies having poor quality in the formation of patterns, thereby achieving an improvement in operation reliability of the semiconductor device.
2. Description of the Prior Art
In the fabrication of semiconductor devices, in particular, highly integrated semiconductor devices, a complex process using a plurality of overlapping light exposure masks is generally used. The layer-to-layer alignment among the light exposure masks used in respective steps of the fabrication process is conducted with respect to a mark having a particular shape.
Such a mark is called "alignment key" or "alignment mark.
The mark is used for the layer-to-layer alignment between different masks or alignment of dies with a mask.
Steppers, which is a step and repeat type illumination device used in the fabrication of semiconductor devices, is a device in which light exposure is conducted as its stage repeatedly performs alignment of a wafer while moving X-Y directions. The stage automatically or manually conducts the alignment of the wafer with reference to an alignment mark.
Since the stage operates mechanically, an error in alignment may be generated while the fabrication process is repetitively carried out. When such an alignment error exceeds its allowable range, the semiconductor devices which are finally obtained may have poor quality.
The overlay accuracy based on misalignment may be adjusted in accordance with the design rule of the semiconductor device. The adjustment ranges from 0 to 30% of a general design rule.
The overlay accuracy measuring mark or overlay measuring mark are used in the same manner as the alignment mark to check whether layers laminated on a semiconductor substrate are accurately aligned with one another.
Conventionally, such an alignment mark or overlay measuring mark is formed on the scribe line of a wafer where no chip is disposed.
The measurement of misalignment using alignment marks is carried out in accordance with either a visual checking method using vernier alignment marks or an automatic checking method using box-in-box or box-in-bar alignment marks. The misalignment is compensated for, based on the result of the measurement.
In the case of a highly integrated semiconductor device, its chip has a dimension of about 15 to 25 mm at its each edge.
For the fabrication of a semiconductor device, a masking process should be conducted tens of times. For this reason, the overlay accuracy measuring mark formed on the scribe line may have indistinct outlines as several subsequent processes are conducted. In severe cases, the overlay accuracy measuring mark itself may be damaged. As a result, inaccurate measurement may be carried out.
For highly integrated semiconductor devices requiring the use of a number of light exposure masks, it is necessary to measure the overlay accuracy between laminated layers. In this case, a plurality of overlay measuring marks are formed on the scribe line. The overlay measuring marks have a size of about 20.times.20 .mu.m.sup.2. For the fabrication of 256 Mega DRAM's, at least 30 overlay measuring marks having the above-mentioned size are required.
In this connection, a conventional method for aligning misaligned micro patterns of a semiconductor device will now be described in conjunction with FIGS. 1 and 2.
FIG. 1 is a schematic view explaining a conventional method for aligning micro patterns of a semiconductor device. On the other hand, FIG. 2 is an enlarged plan view showing measuring marks formed on a die of the semiconductor device of FIG. 1 in accordance with the conventional method.
As shown in FIG. 1, patterns are formed on portions of a semiconductor wafer 1 respectively defined as predetermined dies 2 by sequentially conducting a light exposure process for those dies in a step-and-repeat manner using a stepper.
Alignment marks respectively formed on portions of dies 2 defined as scribe lines on the semiconductor wafer 1 are read by the stepper. Based on the result of the reading, a light exposure mask, which is used for the light exposure process, is aligned with the semiconductor wafer 1.
In this case, the alignment marks have a square shape with a dimension of about 4 .mu.m.
When a misalignment occurs between the die 2A where a pattern will be formed and the die 2B where the pattern has been formed, it is measured using an overlay measuring mark (not shown) formed on one side of the associated alignment mark. The overlay measuring mark consists of an inner measuring mark and an outer measuring mark both having a square shape. The inner measuring mark has a dimension of 10 .mu.m at its each edge whereas the outer measuring mark has a dimension of 20 .mu.m at its each edge.
Thereafter, the distance between the inner and outer measuring marks is measured at their facing edges. That is, distances X1, X2, Y1 and Y2 are measured. Based on the measured distances, degrees of misalignment along X and Y-axes are calculated. The degree of misalignment .delta.X along the X-axis is calculated by the equation: .delta.X=X2-X1 whereas the degree of misalignment .delta.Y along the Y-axis is calculated by the equation: .delta.Y=Y2-Y1.
The measured values for the overlay measuring marks respectively formed at four edges of each die are averaged so as to calculate a misalignment angle .theta. between the semiconductor wafer and light exposure mask.
The inner and outer measuring marks correspond to masks, respectively.
Light having a certain wavelength is irradiated onto the measuring marks. Light beams respectively reflecting from the measuring marks are sensed by a photo image sensor board on which a plurality of photo sensors are arranged in a matrix array.
The sensed light is then measured and analyzed by a measurement device including a photo signal detector and an overlay accuracy data analyzer.
Based on the result of the analysis, degrees of misalignment .delta.X and .delta.Y along the X and Y-axes are calculated (.delta.X=X2-X1; and .delta.Y=Y2-Y1), thereby obtaining correction values for X and Y-axes.
In this case, data obtained for corner portions of each mark is not used in order to avoid a confusion between the data. In this regard, only data obtained for opposite lateral edges of each mark is used as a measured value.
However, the above-mentioned conventional method has various problems.
In accordance with the conventional method, the process can advance normally when alignment marks on the semiconductor wafer are observed. However, where such measuring marks are damaged or lost due to an error occurring upon conducting a desired process such as thin film deposition or etching process, the reading of measuring marks is disenabled over the entire semiconductor wafer. In this case, all dies formed on the semiconductor wafer are considered as having a poor quality. In the case of a 6-inch wafer, about 30 to 40 dies are considered as having poor quality even when one measuring mark is not observed.
Since such a semiconductor wafer, which has alignment marks damaged or lost due to an error in the process as used, is considered as having poor quality in accordance with the above-mentioned conventional method, a reduction in process yield occurs.
An increase in manufacturing cost also occurs because several processes have to be conducted for a semiconductor wafer considered to be a poor-quality product.
In particular, the process error resulting in a damage of alignment marks is mainly generated upon conducting a metal wiring process which is a final process in the fabrication of semiconductor devices. As a result, the process yield is greatly reduced.